1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to SOI semiconductor devices comprising substrate diodes that are formed in the crystalline material of the substrate.
2. Description of the Related Art
The fabrication of integrated circuits requires a large number of circuit elements, such as transistors and the like, to be formed on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips, ASICs (application specific ICs) and the like, CMOS technology is one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed above a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the distance between the source and drain regions, which is also referred to as channel length. Therefore, reducing the feature sizes, and in particular the gate length, of field effect transistors has been an important design criterion.
In view of further enhancing performance of transistors, in addition to other advantages, the SOI (semiconductor- or silicon-on-insulator) architecture has continuously been gaining in importance for manufacturing MOS transistors due to their characteristics of a reduced parasitic capacitance of the PN junctions, thereby allowing higher switching speeds compared to bulk transistors. In SOI transistors, the semiconductor region, in which the drain and source regions as well as the channel region are located, also referred to as the body, is dielectrically encapsulated. This configuration provides significant advantages, but also gives rise to a plurality of issues.
For example, semiconductor elements, such as diodes and the like, may have to be implemented in the substrate material due to certain device requirements, thereby necessitating the formation of appropriate areas in which the substrate material has to be exposed. For example, one important issue in high performance devices, such as microprocessors and the like, is an efficient device-internal temperature management due to the significant heat generation of the transistors. Due to the reduced heat dissipation capability of SOI devices caused by the buried insulating layer, the corresponding sensing of the momentary temperature in SOI devices is of particular importance. Typically, for thermal sensing applications, an appropriate diode structure may be used wherein the characteristic of the diode may permit information to be obtained on the thermal conditions in the vicinity of the diode structure. The sensitivity and the accuracy of the respective measurement data obtained on the basis of the diode structure may significantly depend on the diode characteristic, i.e., on the diode's current/voltage characteristic, which may in turn depend on temperature and other parameters. For thermal sensing applications, it may, therefore, typically be desirable to provide a substantially “ideal” diode characteristic in order to allow a precise estimation of the temperature conditions within the semiconductor device. In SOI devices, a corresponding diode structure, i.e., the respective PN junction, is frequently formed in a substrate window area, i.e., in the substrate material located below the buried insulating layer, above which is formed the “active” semiconductor layer used for forming therein the transistor elements, in combination with other diode structures used for monitoring purposes and the like. Thus, at least some additional process steps may be required, for instance, for etching through the semiconductor layer or a corresponding trench isolation area and through the buried insulating layer in order to expose the crystalline substrate material. On the other hand, the process flow for forming the substrate diode is typically designed so as to exhibit a high degree of compatibility with the process sequence for forming the actual circuit elements, such as the transistor structures.
Although providing substrate diodes in sophisticated SOI semiconductor devices is a promising approach for obtaining reliable temperature data during the operation of the semiconductor device, conventional approaches for forming substrate diodes may result in significant yield losses and, thus, loss of performance in the corresponding substrate window due to the continuous shrinkage of device features, such as transistors, lines and the like. For example, in sophisticated semiconductor devices comprising field effect transistors, the gate length has reached values of approximately 40 nm and less, thereby increasing packing density and also providing superior performance of the individual transistors. Similarly, the wiring network, i.e., the metallization system in combination with an appropriate contact level, has to be appropriately adapted to the increased packing density in the device level of sophisticated semiconductor devices, thereby also requiring contact elements and metal features of reduced lateral dimensions. At the same time, the thickness or height of the various metallization levels also may have to be reduced so as to correspond to the reduced lateral dimensions. During the fabrication of contact levels, i.e., the dielectric material and the corresponding contact elements formed therein that connect to the contact areas of the semiconductor-based circuit elements, and during the fabrication of the metallization layers of the complex metallization system, a plurality of very complex processes, such as lithography processes, deposition and patterning processes, have to be applied, which may have an influence on the characteristics of the substrate diode.
In particular, the metal silicide to be formed in the doped regions of the substrate diodes has a significant influence on the finally obtained diode characteristics, as will be described in more detail with reference to FIG. 1.
FIG. 1 schematically illustrates a cross-sectional view of a semiconductor device 100 in which a substrate diode 150B is formed in the crystalline substrate material 101B of a substrate 101. Furthermore, transistors 150A are formed in and above a semiconductor layer 103, which in turn is formed on a buried insulating material 102. Thus, the semiconductor device 100, or at least the portion shown in FIG. 1, may be considered as an SOI device. It should be appreciated that the semiconductor layer 103 in the manufacturing stage shown in FIG. 1 may represent a material layer having formed therein a plurality of “active” regions or semiconductor regions 103A, in and above which the transistors 150A are formed. The active regions, such as the region 103A, are typically separated laterally from each other by providing appropriate isolation regions 103C, which, for instance, are comprised of silicon dioxide. The transistors 150A may have any appropriate configuration in accordance with the overall device requirements and are typically provided in the form of field effect transistors having gate electrode structures 160, which in turn may comprise a gate dielectric material 162 and an electrode material 161, possibly in combination with a sidewall spacer structure 163. As discussed above, in sophisticated applications, a gate length of the gate electrode structures 160 may be 50 nm and less, thereby also restricting the space between adjacent gate electrodes to a lateral dimension that is the same order of magnitude. Furthermore, the transistors 150A comprise drain and source regions 151A, which are to be understood as highly doped areas in the active region 103A so as to form a PN junction, wherein the lateral and vertical profile depends on the manufacturing process applied to form the drain and source regions 151A. Moreover, a metal silicide 153 is typically provided in the drain and source regions 151A in order to reduce the overall contact resistivity. For example, nickel silicide, possibly in combination with platinum and the like, may be provided in sophisticated applications.
Similarly, the substrate diode 150B comprises a highly doped region 151B that forms a PN junction 151P with the surrounding crystalline substrate material 101B, which may have incorporated therein an appropriate dopant concentration. As will be explained later on in more detail, frequently, the highly doped region 151B may have substantially the same lateral and vertical concentration profile as at least deep drain and source areas of the drain and source regions 151A of the transistors 150A since the regions 151A, i.e., the deeper areas thereof, and the regions 151B are frequently formed on the basis of a common ion implantation process. Similarly, the regions 151B have incorporated therein the metal silicide 153.
Furthermore, in the manufacturing stage shown, a contact level 120 is provided in an intermediate manufacturing stage in which appropriate dielectric materials, such as an etch stop layer 121, for instance provided in the form of a silicon nitride material, in combination with the actual interlayer dielectric material 122, for instance in the form of silicon dioxide and the like, are formed above the transistors 150A and above the substrate diodes 150B and thus also within corresponding substrate openings or windows 1010, which extend through the semiconductor layer 103 and the buried insulating layer 102. As illustrated, contact openings 123A are provided so as to extend through the interlayer dielectric material 122 so as to be aligned to the drain and source regions 151A, depending on the contact regime required, while other contact openings 123G, which may typically be provided in a different width direction, i.e., a direction perpendicular to the drawing plane of FIG. 1, may extend to the gate electrode structures 160. Similarly, contact openings 123B are formed so as to extend into the substrate openings 1010. It should be appreciated that, in the manufacturing stage shown, the openings 123A, 123B, 123G are still separated from any underlying conductive areas by at least a portion of the etch stop layer 121.
The semiconductor device 100 as illustrated in FIG. 1 may be formed on the basis of the following process strategy. After forming the isolation region 103C, thereby also laterally delineating the active regions, such as the semiconductor region 103A, within the semiconductor layer 103, the basic doping is established, for instance, on the basis of ion implantation and the like. To this end, appropriate implantation and masking regimes may be applied. Thereafter, the gate electrode structures 160, that is the electrode material 161, are formed by providing appropriate materials and patterning the same on the basis of complex lithography and etch techniques in order to obtain the desired lateral dimensions in compliance with the overall design rules. Furthermore, additional dopant species may be incorporated into the active region 103A, for instance for forming drain and source extension regions (not shown), counter-doped regions, i.e., regions of increased well dopant concentration and the like, as is required for establishing the complex dopant profile, in particular in the vicinity of channel regions 152, which are positioned between drain and source regions. At any appropriate manufacturing stage, the substrate openings 1010, which extend from the sidewall 101S to the opposite sidewall, are formed by applying appropriate etch techniques wherein, prior to or after forming the openings 1010, or in an intermediate patterning stage, an appropriate base doping, if required, may be implemented into the crystalline substrate material 101B. It should be appreciated that typically the lateral dimensions of the openings 1010 are significantly greater compared to the spacing between closely spaced gate electrode structures 160 in order to provide appropriately dimensioned PN junctions of the diodes 150B and also enable superior connection to contact elements still to be formed within the contact openings 123B. At any appropriate manufacturing stage, in some conventional approaches, the drain and source dopant species for the transistors 150A, for the deep drain and source areas, are incorporated on the basis of an ion implantation process, while concurrently the highly doped regions 151B are formed, thereby avoiding any additional masking and implantation steps for forming the regions 151B. After any anneal processes for activating the dopant species and re-crystallizing implantation-induced damage, the device 100 is prepared for forming the metal silicide regions 153.
It should be appreciated, however, that, after incorporating the dopant species for the drain and source regions 151A and the doped regions 151B, a plurality of cleaning processes have to be applied, for instance for removing resist material, removing contaminants and the like, as is typically required in the complex fabrication processes for forming sophisticated semiconductor devices. In particular during any such processes, a certain degree of material erosion may occur within the opening 101O, which may be substantially comprised of silicon dioxide, at least within the buried insulating material 102, thereby increasingly “widening” the opening 1010, as indicated by 101R. Consequently, the sidewalls 1015 may have been “displaced” after incorporating the dopant species for the regions 151B and prior to actually forming the metal silicide 153. Consequently, when applying the silicidation process, the lateral offset between the PN junction 151P and the metal silicide 153 is reduced due to the material erosion that results in the “recessed” sidewalls 101S. This reduced lateral offset may result in significant alterations of the finally obtained diode characteristics, in particular during the further processing when forming the contact openings 123A, 123G, 123B and adjusting the final cross-sectional shape. Furthermore, the reduced offset of the metal silicide 153 from the PN junction 151P may additionally result in an increased probability of creating short circuits and thus leakage paths, which may also contribute to a reduced performance of the resulting substrate diodes 150B.
After forming the metal silicide 153, which is accomplished on the basis of well-established silicidation techniques, the material or material system of the contact level 120 is formed, for instance, by depositing the etch stop layer 121, for instance using plasma enhanced chemical vapor deposition (CVD), followed by the deposition of the material 122, for instance by CVD, spin-on techniques and the like. If required, a planarization may be applied so as to prepare the device for the subsequent complex patterning process for forming the contact openings 123A, 123G and 123B. During the patterning process, it is etched through the material 122 while using the layer 121 as an efficient etch stop material.
As discussed above, due to the overall reduced dimensions of sophisticated semiconductor devices, the contact openings 123A, 123G also have to be provided with adapted dimensions, which may thus result in high aspect ratio openings, in particular for the openings 123A. In view of providing superior conditions for the subsequent filling in of a contact material, such as tungsten, in combination with appropriate barrier materials, a certain rounding of the upper portions of the contact openings 123A, 123G may be necessary in order to obtain tapered or rounded upper portions 123U. To this end, preferably the etch mask, typically a resist material, possibly in combination with any anti-reflective coating (ARC) material, may be removed after etching through the layer 122 and applying an additional dedicated material removal process, for instance in the form of anisotropic etch processes, ion sputtering processes and the like. As explained before, typically, the contact openings 123B may have significantly greater lateral dimensions, so that an enhanced removal rate may be observed at the bottom of the opening 1010, thereby even “etching” through the layer 121. Consequently, the metal silicide 153 may thus be exposed or at least the corresponding etch stop liner may be significantly reduced, thereby also resulting in undue exposure of the material 153 during the further processing, i.e., during opening the etch stop layer 121. As a consequence of the premature exposure of the material 153, the diode characteristics may be significantly influenced, for instance due to the reduced lateral offset of the material 153 from the PN junction 151P, as discussed above.
In some conventional approaches, superior integrity of the diode characteristics may be achieved by altering the process flow for forming the drain and source regions 151A and the doped regions 151B. That is, a dedicated implantation process may be applied for forming the doped regions 151B with appropriately adapted implantation parameters in order to obtain an increased lateral distribution of the incorporated dopant species. In this manner, the probability of negatively influencing the diode characteristic is significantly reduced, even for a process flow in which the rounded upper areas 123U are to be provided. On the other hand, additional lithography steps in combination with resist removal processes are required in order to separately implement the drain and source regions 151A on the one hand and the doped regions 151B on the other hand. Hence, the overall complexity of the manufacturing process is significantly increased.
In view of the situation described above, the present disclosure relates to manufacturing techniques and semiconductor devices in which substrate diodes may be provided with superior integrity of the diode characteristics, while avoiding or at least reducing the effects of one or more of the problems identified above.